1. Field of the Invention
The present invention generally relates to systems and components that measure phase error between a clock signal and a related data signal, where the measurement must support fast-changing phase error results and where a linear function of phase error is still desired even at these high bandwidth, fast-changing phase error conditions. More particularly, the present invention relates to clock and data recovery systems that create reference clocking signals from an input data signal and also relates to phase error (e.g. jitter) measuring systems that must measure high-frequency jitter components.
2. Description of the Related Art
Phase detectors come in many variants and have been employed in phased-lock loop circuits found in synthesizers, clock and data recovery systems and phase error (e.g. jitter) measuring systems for many years. Each phase detector offers different trade-offs with respect to price and performance. Performance encompasses how well the various phase detectors perform at high speeds, with low jitter, having linear measurements in broadband (wide-ranging frequency) applications.
One of the first separations in phase detectors are that many phase detectors must match each edge of one input signal to a corresponding edge of the other input signal to monitor if one edge is earlier or later than the corresponding edge. These devices require that edges always be present on both signals (e.g. that clocking signals are used). For the application of clock recovery from a data stream or for measuring phase errors (e.g. jitter) in a data stream, this type of phase detector is not appropriate as data streams do not always possess edges at all bit positions. With respect to the present invention, only phase detectors that provide phase error information from data streams are considered relevant.
Phase detectors for data applications, too, have many variants depending on various metrics of performance. For example, for low cost and high level-of-integration reasons, many phase detectors must be implemented in integrated circuit technologies that have only switching transistors present which limits linear-type performance. The most common form of phase detector for data applications are variants of “bang-bang” phase detectors. These types of phase detectors can easily be implemented using digital switching techniques. In this style of detector, it is typical that a data edge is compared to an associated clocking edge and a digital bit or bits are set to one value if the data edge is in advance of the clock edge and the same digital bit or bits are set to another value if the data edge is behind the clock edge. By averaging a sufficient number of such digital bits or bit values, a more smoothly changing phase error estimate can be achieved. This type of detector is called a bang-bang detector because it only has feedback in two (sometimes three) states. That is, ahead or behind (sometimes a third state is introduced giving ahead, behind and hold—no information states). Bang-bang phase detectors can be made to look like linear-enough phase error measurements only when suitable averaging over many clock cells can be afforded. As less and less averaging is employed (as would be required to measure higher fidelity (frequency) phase error signals), the response of such a phase detector starts to look very chunky (e.g. either one state or the other). Hence the name, bang-bang. This behavior is not desirable when high-frequency phase error measurements are necessary as is the case in high-bandwidth clock and data recovery systems or phase error (jitter) measuring systems.
Linear phase detectors at high frequencies also exist. These devices also typically involve averaging; however, the averaged values are now not just a dissimilar number of one bits and zero bits. Instead, partial bits are used by pulse-width modulating the output of the phase detectors. These phase detectors output a pulse that has a width that, when compared to a reference width, not only communicates if the data edge is ahead or behind of the clock edge, but also communicates how far ahead or behind the data edge is with respect to the clock edge. A small difference would indicate a small phase error amount and a large difference would indicate a large phase error amount. These devices have the desirable affect of outputting a linear phase error signal (e.g. not a bang-bang signal) that can be efficiently accumulated (averaged) over only a very short amount of time to provide a linear measure of phase error.
Real-world signals at very high speeds, though, are plagued with the inevitable reality of limited rise and fall times. It is elementary to show that averaging the energy from pulse width modulation such as this becomes non-linear in cases of very short pulses, which can result from such phase detectors. In these cases, the pulse width modulated signal may never reach a full logic level before it must transition again to indicate a short pulse width. This “runt” pulse does not have all the energy that would be present in an ideally square edge. Averaging such a pulse stream would, too, not create the full voltage level ideally indicated by the pulse width measured by the phase detector only because of the non-ideal rise/fall times. This introduces the non-linearity of these devices used in this fashion.
For many systems, such non-linearity is not a problem. After all, the response is still monotonic even if it is not linear and so feedback systems such as phased-lock loops will still operate properly; however, for those applications that are truly relying on linear phase measurement or feedback, these types of phase detectors suffer.
Various techniques have been employed to avoid small output pulses for phase detectors used with clocking signals (e.g. not data applications). Such techniques often rely on dividing the input stream by an integer number (e.g. 2) in frequency using a T-type flip flop and then manipulating the use of the measurement in the application to operate about a point where pulses with plenty of pulse width exist. For example, operating a phased-lock loop at 90-degrees or 180-degrees out of phase so the phase measurements in the in lock state are nominally 50% duty cycle signals. This type of manipulation is not possible in data applications for phase-detectors.
The most direct comparison for the purpose of the state-of-the-art in linear, high-frequency phase detectors for data applications is what is know as the “Hogge” phase detector. This detector operates at very high frequencies (as well as low frequencies) and provides proportional phase error information (it is not a bang-bang phase detector). However, even this detector runs into implementation problems at very, very high frequencies because its design depends on operating with half-bit windows. Half-bit windows for data rate applications of 12.5 Gbit/sec amounts to 40 psec bit windows. In order to make 40 psec pulses that can reach their full 1/0 voltage limits, rise and fall times of less than 15 psec may be required. This is very difficult in today's modern high-speed technologies. Systems that operate by pulse-width modulating full bit windows offer more promise for maintaining good pulse-width shape (and therefore linearity of phase error measurement). A full bit window at 12.5 Gbit/sec amounts to 80 psec so rise/fall times of 30 psec could easily be employed with good linear results. This is more practical in today's integrated circuit and assembly technology.
Therefore, the current state of the art does not offer a linear, ultra-high speed phase detector technology that can be employed to make phase error sitter) measurements in data applications.